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技術名稱 Technology
發明人 Inventor
連國龍, 陳高祥,
所有權人 Asignee 國立臺灣科技大學

專利國家 Country 申請號 Application No. 專利號 Patent No. 中心案號 Serial No.
中華民國 113133235 申請中 1130019TW0
  點閱數:7

技術摘要:
Power-Hardware-in-the-Loop (PHIL) is a kind of real-time simulation, capable of exchanging not just low-voltage, low current signals, but the power required by the power device under test (PDuT). PHIL requires a PDuT to be connected to a real-time digital power network simulator via a power interface (PI). There have been quite a few PIs proposed in the past. Among them, the ideal transformer model (ITM) is the most commonly used due to its ease of implementation. Other PIs such as partial circuit duplication and damping impedance can be considered as an extended version of the ITM. These PIs need to follow a strict impedance ratio between PDuT and the rest of the system prior to the PHIL implementation, which could be a tedious and difficult task. This paper proposed a new PI for PHIL based on multi-dimensional golden section search algorithm, which can eliminate such a constraint. The proposed method has been shown to have wider stability regions when PDuT is a passive device or active one such as an inverter based resource. Moreover, dynamic responses of the proposed method are similar to those of the ITM under stable conditions.

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