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呂學坤

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電機工程系(所)
 
學經歷:
  學歷:
國立台灣大學電機工程研究所博士

經歷:
南亞塑膠公司工務部工程師
長庚紀念醫院儀器處工程師
輔仁大學電子系教授兼系主任
教育部晶片系統設計跨校聯盟中心計畫
DAT聯盟中心召集人
教育部智慧電子整合性人才培育先導型計畫智慧電子應用設計聯盟中心召集人
台灣積體電路設計學會 (TICD) 理事IEEE Taipei Section 財務長



 
專業技術
  超大型積體電路設計與測試、容錯計算、數位 IP 設計
   
專利介紹
  具分散錯誤功能的記憶體及其分散錯誤位元的方法  
為了提升相位變化記憶體製程的良率以及改善可靠度,因此提出了一種新的記憶體編碼字重組機制。當製程上發生......
 

  非揮發性記憶體的故障遮蔽方法  
為了提升非揮發性記憶體製程的良率以及改善可靠度,因此提出了一種新的測試和修復流程。製程上發生的錯誤,......
 

研究計畫
 

教授課程

超大型積體電路測試與可測試設計

國科會計畫

2011內嵌式記憶體自我修復技術與設計自動化 (3/3)
2010無諧波鎖定, 快速鎖定, 全數位式延遲鎖定迴路之研發
2010內嵌式記憶體自我修復技術與設計自動化 (2/3)
2009內嵌式記憶體自我修復技術與設計自動化 (1/3)
2008內嵌式靜態隨機存取記憶體低功率內建自我測試技術之研究
2007內嵌式記憶體有效之內建資源分析與自我修復技術之研究 (2/2)
2006內嵌式記憶體有效之內建資源分析與自我修復技術之研究 (1/2)
2005前瞻無線測試平台與技術分項計畫內嵌式記憶體自我測試、故障診斷與修復技術
2005具易測試性與容錯功能之快速傅立葉轉換器設計技術
2004內嵌式可程式化邏輯模組功能性測試與診斷技術(3/3)
2003內嵌式可程式化邏輯模組功能性測試與診斷技術(2/3)
2003提升私校研發能量行動多媒體網路系統技術之研究發展與應用: 子計劃六之一 (III) 無線多媒體單晶片系統之硬體設計
2002提升私校研發能量 行動多媒體網路系統技術之研究發展與應用: 子計劃六之一 (II) 無線多媒體單晶片系統之硬體設計
2002內嵌式可程式化邏輯模組功能性測試與診斷技術(1/3)
2001計算機記憶體系統之容錯架構與診斷技術之研究
2000多故障模型損壞位準之分析
1999使用OBDD之邊線擴張圖計算網路之端–對可靠度
1998快速傅立葉轉換器之可測試性與容錯設計
 
建教合作計畫
2011 教育部智慧電子整合性人才培育先導型計畫智慧電子應用設計聯盟中心計畫教育部
2010 教育部智慧電子整合性人才培育先導型計畫智慧電子應用設計概論課程開發計畫教育部
2010 超大形積體電路測試核心課程精進計畫-特殊半導體記憶體測試教育部
2010 前瞻晶片系統設計人才培育先導型計畫—設計自動化與測試 (DAT) 聯盟中心 99 年度計畫 教育部
2009 前瞻晶片系統設計人才培育先導型計畫—設計自動化與測試 (DAT) 聯盟中心 98 年度計畫 教育部
2009 教育部前瞻晶片系統設計 (SOC) 學程計畫: 嵌入式系統軟體學程教育部
2008 電子資訊科技於醫療照護之研究與應用 (2/3)  輔仁大學
2008 內嵌式記憶體自我測試、診斷與修復之無線測試平台與技術開發與研究 (4/4)  經濟部
2008前瞻晶片系統設計人才培育先導型計畫—設計自動化與測試 (DAT) 聯盟中心97年度計畫 教育部
2007 內嵌式記憶體自我測試、診斷與修復之無線測試平台與技術開發與研究 (3/4)  經濟部
2007 記憶體測試非同步教材開發 教育部
2007 電子資訊科技於醫療照護之研究與應用 (1/3)  輔仁大學
2007 前瞻晶片系統設計 (SOC) 學程計畫 教育部
2006 內嵌式記憶體自我測試、診斷與修復之無線測試平台與技術開發與研究 (2/4)  經濟部
2005 教育部「超大型積體電路與系統設計教育改進計畫」課程推廣教育部
2005 內嵌式記憶體自我測試、診斷與修復之無線測試平台與技術開發與研究 (1/4)  經濟部
2005 VLSI與系統設計教育改進計畫-EDA聯盟進階測試課程教育部
2004 創造力在積體電路與系統領域之發模式教材發展計畫(第三年) –單晶片系統內嵌式記憶體測試、診斷與修復之創意設計 教育部
2004  VLSI與系統設計教育改進計畫-EDA聯盟測試課程:單晶片系統核心診斷技術 教育部
2004  VLSI與系統設計教育改進計畫-EDA聯盟VTTF 計畫 教育部
2003 大學科技系所人才培育計畫-「積體電路設計課程教學改善計畫」教育部
2003 創造力在積體電路與系統領域之發模式教材發展計畫(第二年) –單晶片系統內嵌式記憶體測試、診斷與修復之創意設計 教育部
2003  VLSI與系統設計教育改進計畫-EDA聯盟測試課程:單晶片系統核心診斷技術 教育部
2003  VLSI與系統設計教育改進計畫-EDA聯盟VTTF 計畫 教育部
2002 創造力在積體電路與系統領域之發模式教材發展計畫(第一年) –單晶片系統內嵌式記憶體測試、診斷與修復之創意設計 教育部
2002  VLSI與系統設計教育改進計畫-EDA聯盟測試課程:單晶片系統核心診斷技術 教育部
2002  VLSI與系統設計教育改進計畫-EDA聯盟VTTF 計畫 教育部
2002  VLSI 改進計劃邏輯診斷技術分項計劃 教育部
2001 單晶片系統邏輯核心效益評估系統 教育部
2000 使用邏輯模擬器作 Stuck-at故障之定位 教育部
2000 教育部第二期 VLSI 改進計劃 教育部
2000 記憶體與邏輯電路診斷技術之研究 Syntest 華騰科技
1998 教育部第一期VLSI 改進計劃 教育部
 
 期刊論文
[1] S. K. Lu, Y. M. Chen, and S. Y. Huang, "Speeding-up Emulation-Based Diagnosis Techniques for Logic Cores," IEEE Design and Test of Computers (SCI, Full paper, to appear)
[2] S. K. Lu and Y. C. Huang, " Improving Reusability of Test Symbols for Test Data Compression," Journal of Information Science and Engineering, (SCI, Full paper, to appear)
[3] S. K. Lu, etc., Efficient BISR Techniques for Embedded Memories Considering Cluster Faults,” IEEE Trans. VLSI Systems, vol. 18, no. 2, pp. 184-193, Feb. 2010. (SCI, Full paper)
[4] S. K. Lu and W. Y. Liu, "Testable Design and BIST Techniques for Systolic Motion Estimators in the Transform Domain," Journal of Electronic Science and Technology,vol. 7, no. 4, pp. 291-296, Dec. 2009 (EI, Full paper)
[5] S. K. Lu, Y. C. Hsiao, C. H. Liu, and C. L. Yang, “Low-Power Built-In Self-Test Techniques for Embedded SRAMs,” VLSI Design, vol. 2007, pp. 1-6, 2007. (SCI, Full paper)
[6] S. K. Lu and C. H. Hsu, “Fault Tolerance Techniques for High Capacity RAMs,” IEEE Trans. Reliabilities, vol. 55, no. 2, pp. 293-306, June 2006. (SCI, Full paper)
[7] S. K. Lu, etc, “Efficient Built-In Redundancy Analysis for Embedded Memories with 2-D Redundancy,” IEEE Trans. VLSI Systems. vol. 14, no. 1, pp. 34-42, Jan. 2006. (SCI, Full paper)
[8] S. K. Lu, H. C. Wu, and Y. C. Tsai, “Multiple Fault Detection and Diagnosis Techniques for Lookup Table FPGA’s,” IEE Proceedings- Computers & Digital Techniques, vol. 152, no. 5, pp. 577-584, Sep. 2005. (SCI, Full paper)
[9] S. K. Lu, J. S. Shih, and S. C. Huang, “Design-for-Testability and Fault-Tolerant techniques for FFT Processo rs,” IEEE Trans. VLSI Systems, vol. 13, no. 6, pp. 732-741, June 2005. (SCI, Full paper)
[10] S. K. Lu and S. J. Yan, “Design and Implementation of a Scalable High-Performance AES Cipher Chip,” Fu Jen Studies, no. 38, pp. 179-196, Dec. 2004.
[11] S. K. Lu, “Defect Level Prediction Using Multi-Model Fault Coverage,” IEICE Transactions on Information and Systems, vol. W87-D, no. 6, June 2004. (SCI, Full Paper, Accepted)
[12] S. K. Lu and Chung-Yin Lee, “Modeling Economics of DFT and DFY: A Profit Perspective,” IEE Proceedings - Computers & Digital Techniques, vol. 151, no. 2, pp. 119-126, Mar. 2004. (SCI, Full paper)
[13] S. K. Lu, “Delay Fault Testing for CMOS Iterative Logic Arrays with a Constant Number of Patterns,” IEICE Transactions on Information and Systems, vol. E86-D, no. 12, pp. 2659-2665, Dec. 2003. (SCI, Full paper)
[14] S. K. Lu, “Built-In Self-Repair Techniques for Embedded RAMs,” IEE Proceedings- Computers & Digital Techniques, vol. 150, no. 4, pp. 201-208, July 2003. (SCI, Full paper)
[15] S. K. Lu, “A Novel Built-In Self-Test Approach for Embedded RAMs,” Journal of Electronic Testing: Theory and Application, vol. 19, pp. 315-324, June 2003. (SCI, Full paper)
[16] H. C. Kao, M. F. Tsai, S. Y. Huang, C. W. Wu, W. F. Chang, and S. K. Lu, “Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults,” Journal of Information Science and Engineering, vol. 19, pp. 571-587, May 2003. (SCI, Full paper)
[17] S. K. Lu and C. Y. Chen, “Design and Implementation of a Two-Dimensional DCT/IDCT Processor for Video Compression Systems,” Fu Jen Studies, no. 36, pp. 49-72. Dec. 2002.
[18] S. K. Lu and J. S. Shi, "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGA’s,” VLSI Design, vol. 15, pp. 397-406, Aug. 2002. (SCI, Full paper)
[19] F. M. Yeh, S. K. Lu, and S. Y. Kuo, "OBDD-based Evaluation of K-terminal Network Reliability ", IEEE Trans. Reliabilities, vol. 51, no. 4, pp. 443-451, Dec. 2002. (SCI, Full paper)
[20] S. K. Lu and M. H. Cheng, “Logic Diagnosis Techniques Based on BIST Environments,” Integrated Circuit Design Magazine, vol. 18, pp. 52-61, Sep. 2001.
[21] S. K. Lu and T. Y. Lee, “A Profit Evaluation System (PES) for VLSI Systems at Early Design Stage,” Fu Jen Studies, no. 34, pp. 69-81. Dec. 2000.
[22] S.-K. Lu and J. S. Shi, "Testing Configurable LUT-Based FPGAs", Journal of Information Science and Engineering, vol. 16, no. 5, pp. 142-153, Sep. 2000. (SCI, Full paper)
[23] J. F. Li, S. K. Lu, S. A. Huang, and C. W. Wu, “Easily Testable and Fault Tolerant FFT Butterfly Networks,” IEEE Trans. Circuits and Systems II, vol. 47, no. 9, pp. 919-929, Sep. 2000. (SCI, Full paper)
[24] S. Y. Kuo, S. K. Lu, and F. M. Yeh, "Determining Terminal-Pair Reliability Based on Edge Expansion Diagrams using OBDD", IEEE Trans. Reliabilities, vol. 48, No. 3, Sep. 1999, pp. 234-246. (SCI, Full paper)
[25] S.-K. Lu, S.-Y. Kuo and C.-W. Wu, “Fault-tolerant interleaved memory systems with two level redundancy,“ IEEE Trans. Computers, pp. 1028-1034, Sep. 1997.
[26] S.-K. Lu, C.-W. Wu and R.-Z. Hwang, “Cell-delay fault testing for iterative logic arrays“, J. Electronic Testing: Theory and Applications (JETTA), pp. 311-316, 1996.
[27] S.-K. Lu, J.-C. Wang and C.-W. Wu, “C-testable design techniques for iterative logic arrays“, IEEE Trans. VLSI Systems, vol. 3, no. 2, pp.146-152, vol. 3, no. 1, Mar. 1995.
[28] S.-K. Lu, C.-W. Wu and S.-Y. Kuo, “Enhancing testability of VLSI arrays for fast Fourier transform“, IEE Proc. Part E, vol. 140, no. 3, pp. 161-166, May. 1993.
 
 研討會論文
[1] S. K. Lu, T. W. Chang, and H. Y. Hsu, "Efficient Built-In Self-Repair Techniques for Yield Enhancement of 3D Random Access Memories," in Proc. Int'l Conf. on Dependable Systems and Networks (DSN), June 2011. (to appear)
[2] H. Y. Hsu, S. K. Lu, and S. Y. Kuo, "High-Speed Testing Techniques for Content Addressable Memories," in Proc. Int'l Conf. on Dependable Systems and Networks (DSN), June 2011. (to appear)
[3] S. K. Lu and Zhen-Qun Quan, "Concurrent Error Detection Techniques for Array Multipliers," in Proc. 2011 Intelligent Living Technology Conference (to appear)
[4] S. K. Lu, J. Y. Wang, and Y. M. Tsai, "Yield Enhancement Techniques for Multiple Repairable Memory Cores," 4th VLSI Test Technology Workshop (VTTW2010), Aug. 2010.
[5] M. Y. Dong, S. H. Yang, and S. K. Lu, "Testable and Built-In Self-Test Techniques for Motion Estimation Computing Arrays," in Proc. IEEE Eleventh Workshop on RTL and High-Level Testing, Dec. 2010. (to appear)
[6] Z. Y. Wang, Y. M. Tsai, Y. C. Hsiao, and S. K. Lu, “Wireless Built-In Self-Repair Techniques for Embedded RAMs, 8th IEEE Int’l Conf. ASIC, pp. 573-576, Oct. 2009.
[7] Z. Y. Wang, Y. M. Tsai and S. K. Lu, "Built-In Self-Repair Techniques for Heterogeneous Memory Cores,” in Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2009), pp. 69-74, Nov. 2009.
[8] S. K. Lu and H. S. Fu, “Low-Complexity Computation Techniques for Block Matching Motion Estimation,” in Proc. IEEE International Symposium on Consumer Electronics (ISCE 2009), pp. 681-682, May 2009.
[9] S.K. Lu, H. M. Chuang, G. Y. Lai, B. T. Lai, and Y. C. Huang, "Efficient Test Pattern Compression Techniques Based on Complementary Huffman Coding," in Proc. 3rd VLSI Test Technology Workshop (VTTW2008), July 2009.
[10] S. K. Lu and G. Q. Lin, “Built-In Self-Repair Techniques for Content Addressable Memories,” in Proc. IEEE Int’l Symp. on VLSI Design, Automation and Test (VLSI-DAT) pp. 267-270, Apr. 2009.
[11] S. K. Lu, W. Y. Liu, J. Y. Huang, and J. J. Hong, “Testable Design and BIST Techniques for Systolic Motion Estimators in the Transform Domain,” in Proc. IEEE Int’l Conf. on Testing and Diagnosis (ICTD2009), pp. 1-4, Apr. 2009.
[12] S. K. Lu, H. M. Chuang, G. Y. Lai, B. T. Lai, and Y. C. Huang, “Efficient Test Pattern Compression Techniques Based on Complementary Huffman Coding,” in Proc. IEEE Int’l Conf. on Testing and Diagnosis (ICTD2009).
[13] P. Y, Yeh, B. Y. Yeh, S. Y. Kuo, and S. K. Lu, "Scalable arithmetic cells for iterative logic array," in Proc. IEEE Int'l Conf. on Electrical and Computer Engineering, Dec. 2008, pp. 325-330.
[14] P. Y, Yeh, B. Y. Yeh, S. Y. Kuo, and S. K. Lu, "Novel C-Testable Design for H.264 Integer Motion EWstimation," in Proc. IEEE Int'l Conf. on Electrical and Computer Engineering, Dec. 2008, pp. 735-740.
[15] S. K. Lu, G. Q. Lin, and S. Y. Kuo, ”Yield Enhancement Techniques for Content-Addressable Memories,” in Proc. IEEE/IFIP Int. Conf. on Dependable Systems and Networks (DSN), pp. 27-28, June 2008.
[16] M. Y. Dong, S. H. Yang, and S. K. Lu, “Design-for-Testability Techniques for Motion Estimation Computing Arrays,” in Proc. Int. Conf. Comm., Circuits, and Systems, pp. 161-164, May 2008.
[17] S. K. Lu, Y. C. Hsiao, and C. L. Yang, “Efficient BISR Techniques for Embedded Memories Considering Cluster Faults,” Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2007), pp. 224-231, Dec. 2007.
[18] C. L. Yang and S. K. Lu, “Modified Essential Spare Pivoting Algorithm for Embedded Memories with Global Block-Based Redundancy,” Proc. 16th VLSI/CAD Symposium, Aug. 2007.
[19] S. K. Lu, M. Y. Dong and S. H. Yang, “Architectures and Testable Design Techniques for Motion Estimation Computing Arrays,” 1st VLSI Test Technology Workshop, July 2007.
[20] C. L. Yang and S. K. Lu, “Global Block-Based Built-In Self-Repair Techniques for Embedded SRAMs,” in Proc. IASTED Conf. on "Circuits, Signals and Systems (CSS 2007), pp. 76-79, July 2007.
[21] S. K. Lu, J. H. Lieo, J. L. Yang, and Y. C. Hsao” Low-Power Built-In Self-Test Techniques for Embedded SRAMs,” in Proc. 7th Workshop on RTL and High-Level Testing, (to appear)
[22] S. K. Lu, T. Y. Chen, and W. Y. Liu, “Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits,” in Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2006), pp. 97-104, Dec. 2006.
[23] M. W. Wu, Y. N. Huang , I. Y. Chen3, S. K. Lu, and S. Y. Kuo, “A Scalable Port Forwarding for P2P-based Wi-Fi Applications,” in Proc. IEEE Int’l Conf. on Wireless Algorithms, Systems and Applications (WASA’06), Xi’an, Aug. 2006.
[24] S. K. Lu, C. L. Yang, and H. W. Lin, “Efficient BISR Techniques for word-Oriented Embedded Memories with Hierarchical Redundancy, in Proc. IEEE Int’l Conf. on Computer and Information Science (ICIS2006), pp. 355-360, July 2006.
[25] S. K. Lu, W. Y. Liu, and T. Y. Chen, Efficient BIST Techniques for Two-Dimensional DCT/IDCT Processors,” in Proc. 2006 Intelligent Living Technology Conference, pp. 33-37, June 2006.
[26] P. Y. Yeh, B. Y. Yeh, I. Y. Cheng*, S. Y. Kuo, and S. K. Lu, “Testable Design Techniques for Variable Block Size Motion Estimator Used in H.264/AVC,” 5th International Conference on Instrumentation, Measurement, Circuits, and Systems (IMCAS '06), Apr. 16-18, 2006.
[27] S. K. Lu and M. Y. Dong, “Efficient Built-In Self-Test Techniques for Sequential Fault Testing of Iterative Logic Arrays,” 5th International Conference on Instrumentation, Measurement, Circuits, and Systems (IMCAS '06), Apr. 16-18, 2006.
[28] S. K. Lu, H. C. Wu, and Y. C. Tsai, “Fault Grading and Test Configuration Generation for Embedded FPGAs,” Proc. 16th VLSI/CAD Symposium, Aug. 2005.
[29] S. K. Lu and S. C. Huang, “Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs,” Proc. 16th VLSI/CAD Symposium, Aug. 2005.
[30] S. K. Lu, Y. C. Tsai, and S. C. Huang, “A BIRA Algorithm for Embedded Memories with 2-D Redundancy,” Proc. Int’l Workshop on Memory Technology, Design and Testing (MTDT’05), pp. 121-126, Aug. 2005.
[31] S. K. Lu, and S. C. Huang, “A Built-In Self-Repair Compiler for Embedded Memories,” in Proc. 6th Workshop on RTL and High-Level Testing, pp. 180-183, July 2005.
[32] S. K. Lu, H. C. Wu, and Y. C. Tsai, “Fault Detection and Diagnosis Techniques for Embedded FPGA’s,” Proc. Asian Test Symposium, pp. 414-419, Nov. 2004.
[33] S. K. Lu, H. W. Lin, Y. C. Tsai, and K. H. Wang, “Efficient Built-In Redundancy Analysis for Embedded Memories with 2-D Redundancy,” Proc. Int’l SOC Design Conf., pp. 380-384, Oct. 2004.
[34] S. K. Lu and S. C. Huang, “Built-In Self-Test and Repair (BISTR) Techniques for Embedded RAMs,” Proc. Int’l Workshop on Memory Technology, Design and Testing (MTDT’04), pp. 60-64, Aug. 2004.
[35] S. K. Lu and M. J. Lu, “Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model,” Proc. IEEE Int’l Conf. Electronic Design, Test and Applications (DELTA2004), pp. 81-84, Jan. 2004.
[36] S. K. Lu, Chien-Hung Yeh and Han-Wen Lin, “Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors,” Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2004), pp. 321-326, Mar. 2004.
[37] S. K. Lu, H. C. Wu, and Y. C. Tsai, “Efficient Fault Simulation Techniques and Test Configuration Generation for Embedded FPGAs,” Proc. 46th IEEE Midwest Symposium on Circuits and Systems,” Dec. 2003.
[38] S. K. Lu and Y. C. Tsai, “Built-In Self-Repair Techniques for High-Density Embedded RAMs,” VLSI/CAD Symposium, Aug. 2003.
[39] S. K. Lu, J. L. Chen, C. W. Wu, W. F. Chang, and S. Y. Huang, “Combinational Circuit Fault Diagnosis Using Logic Emulation,” Proc. Int. Symp. Circuits and Systems, pp. V-549-V-552, May 2003.
[40] S. K. Lu and M. J. Lu, “Testing Iterative Logic Arrays for Delay Faults with a Constant Number of Patterns,” Proc. International Symposium on Electronic Materials and Packaging, pp. 492-498, Dec. 2002.
[41] S. K. Lu and Jen-Hong Yeh, “Enhancing Delay Fault Testability for Iterative Logic Arrays,” Proc. Pacific Rim International Symposium on Dependable Computing, pp. 283-290, Dec. 2002.
[42] S. K. Lu and Chung-Yang Chen, “Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs,” Proc. Asian Test Symposium, pp. 236-241, Nov. 2002.
[43] S. K. Lu and Jen-Hong Yeh, “Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks,” Proc. Asian Test Symposium, pp. 230-235, Nov. 2002.
[44] C. H. Hsu and S. K. Lu, “Fault-Tolerance Design of Memory Systems Based on DBL Structures,” Proc. IEEE Asia-Pacific Conference on Circuits and Systems, Oct. 2002, pp. 221-224.
[45] C. H. Hsu, S. K. Lu, and S. Y. Kuo, “Novel Fault-Tolerant Techniques for High Capacity RAMs,” Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2001), pp. 11--18, Seoul, Korea, Dec. 2001.
[46] I. M. Chen, S. K. Lu, “Logic Diagnosis Based on Hardware Emulator,” Proc. 2001 VLSI/CAD Workshop, Taoyuan, Taiwan, Aug. 2001.
[47] C. H. Hsu, S. K. Lu, and M. H. Chen, “A Novel Column Block-Based Fault-Tolerant Memory System,” Proc. 2001 VLSI/CAD Workshop, Taoyuan, Taiwan, Aug. 2001.
[48] S. K. Lu, T. Y. Lee, and C. W. Wu, “A Profit Evaluation (PES) for Logic Cores at Early Design Stage,” Proc. Int. Conf. Electronic Circuits and Systems (ICECS2001), pp. 1491-1494.
[49] S. K. Lu and Chih-Hsien Hsu, “Built-In Self-Repair for Divided Word Line Memory,” Proc. Int. Symp.Circuits and Systems (ISCAS2001), pp. IV13-IV16.
[50] S. K. Lu and Jen-Sheng Shih, and Cheng-Wen Wu, “BIST and Diagnosis of Fully Logic Blocks in FPGAs,” Proc. 2000 VLSI/CAD Workshop, pp. 413-416, KengDing, Taiwan, Aug. 2000.
[51] S. K. Lu and Chih-Hsien, “Built-In Self-Repair for Divided Word Line Memory,” Proc. 2000 VLSI/CAD Workshop, pp. 405-408, KengDing, Taiwan, Aug. 2000.
[52] S. K. Lu, J. S. Shih, and C. W. Wu, “A Testable/Fault-Tolerant FFT Processor Design,” Proc. Asian Test Symposium, pp. 429-433, Dec. 2000.
[53] S. K. Lu, J. S. Shih, and C. W. Wu, "Built-In Self-Test and Fault Diagnosis for Lookup Table FPGAs,” Proc. Int. Symp. Circuits and Systems (ISCAS), vol. 1, pp. 80-83, May 2000.
[54] S. K. Lu and C. W. Wu, "Defect Level Prediction Using Multi-Model Fault Coverage", Proc.Asian Test Symp. (ATS), Shanghai, Nov. 1999.
[55] S. K. Lu and C. W. Wu, "Defect Level Prediction Using Multi-Model fault Coverage” Proc. 10th Design/CAD Symp., Nantou, pp. 195-198, Aug. 1999.
[56] S. K. Lu, J. S. Shih, and C. W. Wu, "Testing Configurable LUT-Based FPGA’s,” Proc. 10th Design/CAD Symp., Nantou, pp. 171-174, Aug. 1999.
[57] S. K. Lu and C. W. Wu, "A Novel Approach to Testing LUT-Based FPGAs", Proc. Int. Symp.Circuits and Systems (ISCAS), vol. 2, pp. 69-72, Orlando, May 1999.
[58] J. F. Li, S. A. Arn, S. K. Lu and C. W. Wu, "Fault tolerant FFT butterfly network design", Proc VLSI/CAD Workshop, pp. 403-407, Nantou, Taiwan, Aug. 1998.
[59] S. K. Lu and C. W. Wu, “VLSI design of RSA public-key cryptosystem”, Proc. 1997 ISIC Symposium, pp. 68-71, Singapore, Sep. 1997.
[60] Y.-N. Rau, W.-Y. Tseng, S.-K. Lu and S.-Y. Kuo, “A 155.52 Mhz SVDCO-based all digital clock recovery circuit for ATM Applications“, Proc. 1996 VLSI/CAD Workshop, pp. 123-126, Shiemen, Taiwan, Aug. 1996.
[61] S.-K. Lu, C.-W. Wu and S.-Y. Kuo, “On fault-tolerant FFT butterfly network design”, Proc. Int. Symp. Circuits and Systems (ISCAS), vol. 2, pp. 69-72, Atlanta, May 1996.
[62] S. K. Lu, S. Y. Kuo and C. W. Wu, “Design and Evaluation of Fault-Tolerant Interleaved Memory Systems”, Proc. Asian Test Symp. (ATS), Nara, Nov. 1994, pp. 354-359.
[63] S.-K. Lu, C.-W. Wu and S.-Y. Kuo, “Design of easily testable VLSI arrays for discrete cosine transform“, Proc. IEEE 26th Ann. Asilomar Conf. Signals, Systems, and Computers“, Pacific Grove, Oct. 1992.
[64] S.-K. Lu, C.-W. Wu and S.-Y. Kuo, “Testable design of systolic arrays for discrete cosine transform, Proc. VLSI/CAD Workshop, pp. 228-237, Nantou, Taiwan, Mar. 1992.
[65] C.-W. Wu and S.-K. Lu, “Designing self-testable cellular arrays”, Proc. IEEE Int. Conf. Computer Design (ICCD), pp. 110-113, Cambridge, Massachusetts, Oct. 1991.
[66] C.-W. Wu and S.-K. Lu, “Architecture-Specific Computer-Aided Testing”, Proc. Sino- German CAD/VLSI Workshop, pp. 34-43, Tainan, Taiwan, Sep. 1991.
[67] C.-W. Wu, S. K. Lu and J.-C. Wang, “Built-in self-test of iterative logic arrays”, Proc. Int. Electron Devices and Material Symposium (EDMS), pp. 485-488, Hsinchu, Taiwan, Nov. 1990.
 
 專利.專書.技術報告
[1] 呂學坤 (2007-2008): 內嵌式記憶體有效之內建資源分析與自我修復技術之研究, 國科會專題研究計畫成果報告
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[5] 呂學坤 (2004): 內嵌式可程式化邏輯模組功能性測試與診斷技術(2/3), 國科會專題研究計畫成果報告
[6] 呂學坤 (2003): 內嵌式可程式化邏輯模組功能性測試與診斷技術(1/3), 國科會專題研究計畫成果報告
[7] 呂學坤 (2002):計算機記憶體系統之容錯架構與診斷技術之研究, 國科會專題研究計畫成果報告
[8] 呂學坤 (2001): 記憶體與邏輯電路診斷技術之研究期末報告,華騰科技
[9] 呂學坤 (2000): 多故障模型損壞位準之分析。國科會專題研究計畫成果報告
[10] 呂學坤 (1999): 使用邊線擴張圖計算網路之端對可靠度。國科會專題研究計畫成果報告
[11] 呂學坤 (1998): 快速傅立葉轉換器之可測試性與容錯設計。國科會專題研究計畫成果報告
[12] 呂學坤 (1998): IC 製造機台 SPC 技術研究與實現。中山科學研究院產學計畫成果報告
[13] 呂學坤、鄭淑蘭;呼吸治療設備,合記圖書,1989