期刊論文

• Yung-Hui Chung* and Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2217–2226, Nov., 2010.
• Yung-Hui Chung*, Meng-Hsuan Wu and Hung-Sung Li, "A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS," IEEE Trans. on Circuits and Systems I, vol. 62, no. 1, pp.10-18, Jan. 2015.
• Yung-Hui Chung* and Jieh-Tsorng Wu, “A 16-mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” IEEE Trans. on VLSI Systems, vol. 23, no. 3, pp. 557-566, Mar. 2015.
• Yung-Hui Chung*, Chia-Wei Yen, and Meng-Hsuan Wu, "A 24-uW 12-b 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS," IEEE Trans. on VLSI Systems, vol. 24, no. 11, pp. 3334-3344, Nov. 2016.
• Yung-Hui Chung*, Cheng-Hsun Tsai, and Hsuan-Chih Yeh, "A 5-bit 1-GS/s Binary-Search ADC in 90-nm CMOS," Microelectronics Journal, vol. 63, pp.131-137, Apr. 2017
• Yung-Hui Chung* and Chia-Wei Yen, "An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS," IEEE Trans. on VLSI Systems, vol. 25, no. 12, pp. 3434-3443, Dec. 2017.
• Yung-Hui Chung*, Chia-Wei Yen, and Pei-Kang Tsai, "A 12-bit 10-MS/s SAR ADC with a Binary-Window DAC Switching Scheme in 180-nm CMOS," International Journal of Circuit Theory and Applications, vol. 46, no. 4, pp. 748-763, Apr. 2018. https://doi.org/10.1002/cta.2424
• Yung-Hui Chung*, Wei-Shu Rih, and Che-Wei Chang, "A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55nm CMOS," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 8, pp.999-1003, Aug. 2018.
• Yung-Hui Chung*, Chia-Wei Yen, Pei-Kang Tsai, and Bo-Wei Chen, “A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme,” IEEE Trans. on VLSI Systems, vol. 26, no. 10, pp. 1989-1998, Oct. 2018.
• Yung-Hui Chung* and Ya-Mien Hsu, "A 12-bit 100-MS/s Subrange SAR ADC with a Foreground Offset Tracking Calibration Scheme," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 7, pp. 1094-1098, Jul. 2019.
• Yung-Hui Chung*, Qi-Feng Zeng, and Yi-Shen Lin, “A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 2, pp. 358–368, Feb. 2020.
• Yung-Hui Chung* and Wei-Shu Rih, “A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs. vol. 67, no. 4, pp. 645–649, Apr. 2020.
• Yung-Hui Chung*, Chia-Hui Tien, and Qi-Feng Zeng, “A 16-bit Calibration-Free SAR ADC with Binary-Window and Capacitor-Swapping DAC Switching Schemes,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 69, no. 1, pp. 88–99, Jan. 2022

會議論文

• Y.-H. Chung and J.-T. Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 137–140.
• Y.-H. Chung and J.-T. Wu, “A 16mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” in VLSI Circuits Symp. Dig., Jun. 2011, pp. 128–129.
• Meng-Hsuan Wu, Yung-Hui Chung and Hung-Sung Li, "A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC using Capacitor-Swapping Technique," to appear in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2012.
• Yung-Hui Chung, “The Swapping Binary-Window DAC Switching Technique for SAR ADCs,” in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2013, pp.2231-2234.
• Yung-Hui Chung, Meng-Hsuan Wu, and Hung-Sung Li, “A 24uW 12b 1MS/s 68.3dB SNDR SAR ADC with Two-Step Decision DAC Switching,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2013.
• Yung-Hui Chung, “Perturbation-Based Digital Background Calibration Technique for Pipelined ADCs,” in Proc. of IEEE Int. Sym. on Circuits and Systems (ISCAS), 2014.
• Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s 2.7-mW Binary-Search ADC in 90nm Digital CMOS," in Proc. IEEE SOC Conference, pp. 25-29, Sep. 2015.
• Yung-Hui Chung and Chia-Wei Yen, "A PVT-Tracking Metastability Detector for Asynchronous ADCs," in Proc. of IEEE Int. Sym. On Circuits and Systems (ISCAS), 2016, pp.1462-1465.
• Yung-Hui Chung, Cheng-Hsun Tsai, and Hsuan-Chin Yeh, "A 5-b 1-GS/s Binary-Search ADC in 90nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016, pp.334-337.
• Yung-Hui Chung and Song-Yo Shih, “A 10-bit 100-MS/s SAR ADC With Capacitor Swapping Technique in 90-nm CMOS,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2017, pp. 1-4.
• Yung-Hui Chung and Hua-Wei Tseng, “A 10-bit 100-MS/s 2b/cycle-Assisted SAR ADC in 180nm CMOS,” in Proc. of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Oct. 2017, pp. 1-2.
• Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, and Wei-Shu Rih, “A 12-bit 160-MS/s Ping-Pong Subranged-SAR ADC in 65nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 5-6. (Best Paper Award)
• Yung-Hui Chung and Wei-Shu Rih, “A 6-bit 1.6-GS/s Domino-SAR ADC in 55nm CMOS,” in Proc. of International SoC Design Conference (ISOCC), Nov. 2017, pp. 216-217.
• Yung-Hui Chung, Hsuan-Chih Yeh, and Che-Wei Chang, 'A 10b 160-MS/s Domino-SAR ADC in 90nm CMOS,' in Proc. of IEEE International Symposium on Next Generation Electronics (ISNE), May 2018, pp.1-2.
• Yung-Hui Chung, Hung-Po Ni, Yi-Shen Lin, and Qi-Feng Zeng, "A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2018, pp.34-37.
• Yung-Hui Chung, Chia-Yi Hu, and Che-We Chang, “A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2018, pp. 243–246.
• Yung-Hui Chung and Min-Sheng Chiang, "A 12-bit Synchronous-SAR ADC for IoT Applications," IEEE Int. Sym. on Circuits and Systems (ISCAS), May 2019, pp. 1-5.
• Yung-Hui Chung, “A 12-bit Domino ADC with a Background Offset Calibration Scheme,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019, pp. 9-12
• Yung-Hui Chung, Qi-Feng Zeng, and Chia-Hui Tien, “A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019, pp. 5-8.
• Yung-Hui Chung and Qi-Feng Zeng, “A 12-bit 100-kS/s SAR ADC for IoT Applications,” IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Aug. 2020, pp. 1-4.
• Bo-Wei Chen, Yung-Hui Chung, and Chia-Ming Tsai, "An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique," accepted by IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), 2021.
• Yung-Hui Chung, Jia-Fong Shih and Yu-Hsiang Wang, "A Resistor-Less CMOS Bandgap Reference with High-Order Temperature Compensation," accepted by IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2021
• Yung-Hui Chung, Chia-Hui Tien, and Qi-Feng Zeng, “A 16-bit Calibration-Free SAR ADC with Binary-Window and Capacitor-Swapping DAC Switching Schemes,” accepted by IEEE ISICAS 2021